Executive Summary This project successfully extends the Gigaflow Virtual Switch (GVS) (find out more here) framework to enable hardware acceleration on SmartNICs, specifically targeting NetFPGA platforms. The work bridges the gap between software-defined networking (SDN) and hardware acceleration by implementing a complete pipeline from P4 code compilation to bitstream deployment and runtime rule management. Enhanced Gigaflow Virtual Switch (GVS) The core contribution of this project is the extension of the Gigaflow Virtual Switch to support hardware acceleration through SmartNIC offload. The gvs-offload maintains full backward compatibility with the software-only implementation while adding comprehensive hardware acceleration capabilities. ...

Abstract This project aims to extend the existing P4sim module integrated within the ns-3 network simulator by implementing control plane functionalities. The P4sim currently supports the simulation of P4-programmable data planes in ns-3, providing a powerful environment for research and development in programmable networking. This project bridges that gap by integrating a control plane to support P4 Runtime, like changing the openconfig-interfaces, the ethernet augments and other runtime configurable features. The enhancements will improve the realism and usability of the simulator for research and experimentation involving P4 ...

Google Summer of Code 2025 Final Report Project Repository: SpliDT Codebase Project Overview SpliDT is a switch-native compiler framework that enables stateful decision tree inference directly in programmable switches, bringing real-time machine learning into the network data plane. SpliDT compiles high-performance decision tree models to enable detection and observability of security-significant flow behaviors across diverse traffic workloads. A major challenge in deploying decision trees in this environment is the limited stateful memory of ASIC chips, which makes it impossible to store multiple packet features simultaneously. SpliDT solves the issue with Partitioned Decision Trees (PDTs). Instead of evaluating all features simultaneously, the tree is split into smaller subtrees, each handling only top k-features at a time. Flows are guided across subtrees using Subtree IDs (SIDs), ensuring that all features are eventually considered without exceeding hardware limits. This design reduces memory usage, removes latency overheads, and maintains classification accuracy, while making the system scalable and efficient. ...

Abstract There are many situations where it is more useful to have all possible outputs from a P4 simulation rather than only a single one. One such instance is diff testing. Diff testing compares the outputs of packets sent through the switch and BMv2. By providing multiple outputs to the packets that get sent to BMv2, it provides more accurate portrayal of the the correctness of the switch’s behavior. Multiple allowed behaviors usually arise from various multi-path constructs (e.g. ECMP, WCMP, or perhaps LAGs) usually modeled as action profiles/selectors in P4. BMv2 currently allows users to set a mode determining action selector behavior, like round robin which means that every time you send in the same packet, it should result in the next possible outcome (eventually wrapping around). ...

Abstract This project aims to develop a code formatter for P4. While the reference P4 compiler (P4C) provides foundational components, such as an AST/IR parser and a pretty printer, key gaps remain. The current AST/IR does not retain comments from the original source code, and the pretty printer lacks the flexibility required for common formatting options. This project addresses these issues by enhancing the AST/IR to preserve comments and adapting the pretty printer to support customizable formatting rules, ultimately creating a functional P4 code formatter for the first time. ...

Abstract As the P4 use cases on the NIC side increase, so does the need for a P4 simulator that supports Portable NIC Architecture (PNA). Currently, the BMv2 simulator only supports the v1model and Portable Switch Architecture (PSA) specifications. This project aims to integrate a minimal core subset of the PNA into the BMv2 and the P4C. The PNA Architecture Block Diagram is shown in below: Goals Create a new target in BMv2 supporting the core subset of PNA Create a new P4C backend for the new BMv2’s PNA NIC target Design test cases to ensure the PNA NIC target is working Results The project successfully creates a new target in BMv2 to support PNA and a corresponding backend in P4C. A test case is implemented to ensure the new PNA NIC target can forward the packets between interfaces. ...

Project Overview The primary objective of this project was to improve the documentation infrastructure of the P4 Compiler (p4c). This involved upgrading tools, automating deployment processes, enhancing the user interface, and ensuring that the documentation is both comprehensive and accessible. The project was aimed at making the documentation easier to maintain and more useful for both developers and users of the P4 language. ...

Abstract Kubernetes has recently introduced a container checkpoint/restore (C/R) feature to enable the creation of stateful snapshots for running containers. This feature allows containers to be restarted from checkpoints in different pods, enabling use cases such as live migration of microservices. However, preserving established TCP connections during migration is challenging because Kubernetes dynamically allocates IP addresses to Pods in the cluster. As a result, the restored container will run with a different IP address after migration, while clients will continue to send packets to the old IP address. This project aims to address this problem by developing a P4-based load balancer that keeps track of established TCP connections and routes application traffic to the correct IP address after container migration. ...