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Abstract P4Pi brings P4 programming to a Raspberry Pi, making programmable data planes accessible for teaching and research on hardware costing under £100. Planter converts trained machine-learning models into P4 programs and match–action table entries, enabling inference to run directly in the packet-processing path. The two could not be used together. Planter’s low-cost target support ended at BMv2, which suits functional validation but not sustained traffic, and it had no adapter for p4c-dpdk — the compiler backend for P4Pi’s higher-performance DPDK pipeline. ...

Abstract P4 Traffic Control (P4TC) is a Linux kernel subsystem that runs P4 programs in the networking data path - either in software via eBPF, or offloaded to hardware like SmartNICs. Its userspace runtime API (libp4tctrl) is a C library that requires manual memory management, pointer arithmetic, and raw byte handling. This project built complete, high-level API wrappers in Python and Rust that let developers manage P4 objects (tables, externs) and event subscriptions using native language idioms. Both wrappers handle object allocation/deallocation, callback bridging, response parsing, and schema-driven type decoding - exposing a clean, idiomatic API in each language. ...

Abstract This project reworks the switch datapath of P4Sim, the P4 switch module for the ns-3 network simulator. Before this work, packets reached the channel through an extra port layer, switch links reused the generic CSMA/P2P channel models, and the queues were drained by a timer that polled them regardless of port state. The result was an indirect datapath and a scheduler that did not track when a port was actually free to send. ...

Abstract P4-SpecTec1 is a mechanization toolchain for the P4 programming language. It provides a domain-specific language for writing formal specifications in the form of algorithmic inference rules. In March 2026, P4-SpecTec was conditionally accepted by the P4 core team as the official language specification authoring toolchain for P4. However, P4-SpecTec currently lacks accessible learning resources: new users face a steep learning curve in understanding how to use the tool in practice. ...

Abstract This project introduces a structured, protobuf-based packet tracing facility to BMv2, the reference software switch for the P4 ecosystem. Previously limited to unstructured textual logs, BMv2 can now record and expose per-packet trace data - including applied tables, matched entries, and executed actions - in a programmatic format with txtproto serialization support. Alongside this core observability enhancement, this project successfully integrated Bazel build support to streamline dependency management and modernized the C++ codebase to improve overall performance and maintainability. ...

Executive Summary This project successfully extends the Gigaflow Virtual Switch (GVS) (find out more here) framework to enable hardware acceleration on SmartNICs, specifically targeting NetFPGA platforms. The work bridges the gap between software-defined networking (SDN) and hardware acceleration by implementing a complete pipeline from P4 code compilation to bitstream deployment and runtime rule management. Enhanced Gigaflow Virtual Switch (GVS) The core contribution of this project is the extension of the Gigaflow Virtual Switch to support hardware acceleration through SmartNIC offload. The gvs-offload maintains full backward compatibility with the software-only implementation while adding comprehensive hardware acceleration capabilities. ...

Abstract This project aims to extend the existing P4sim module integrated within the ns-3 network simulator by implementing control plane functionalities. The P4sim currently supports the simulation of P4-programmable data planes in ns-3, providing a powerful environment for research and development in programmable networking. This project bridges that gap by integrating a control plane to support P4 Runtime, like changing the openconfig-interfaces, the ethernet augments and other runtime configurable features. The enhancements will improve the realism and usability of the simulator for research and experimentation involving P4 ...

Google Summer of Code 2025 Final Report Project Repository: SpliDT Codebase Project Overview SpliDT is a switch-native compiler framework that enables stateful decision tree inference directly in programmable switches, bringing real-time machine learning into the network data plane. SpliDT compiles high-performance decision tree models to enable detection and observability of security-significant flow behaviors across diverse traffic workloads. A major challenge in deploying decision trees in this environment is the limited stateful memory of ASIC chips, which makes it impossible to store multiple packet features simultaneously. SpliDT solves the issue with Partitioned Decision Trees (PDTs). Instead of evaluating all features simultaneously, the tree is split into smaller subtrees, each handling only top k-features at a time. Flows are guided across subtrees using Subtree IDs (SIDs), ensuring that all features are eventually considered without exceeding hardware limits. This design reduces memory usage, removes latency overheads, and maintains classification accuracy, while making the system scalable and efficient. ...

Abstract There are many situations where it is more useful to have all possible outputs from a P4 simulation rather than only a single one. One such instance is diff testing. Diff testing compares the outputs of packets sent through the switch and BMv2. By providing multiple outputs to the packets that get sent to BMv2, it provides more accurate portrayal of the the correctness of the switch’s behavior. Multiple allowed behaviors usually arise from various multi-path constructs (e.g. ECMP, WCMP, or perhaps LAGs) usually modeled as action profiles/selectors in P4. BMv2 currently allows users to set a mode determining action selector behavior, like round robin which means that every time you send in the same packet, it should result in the next possible outcome (eventually wrapping around). ...

Abstract This project aims to develop a code formatter for P4. While the reference P4 compiler (P4C) provides foundational components, such as an AST/IR parser and a pretty printer, key gaps remain. The current AST/IR does not retain comments from the original source code, and the pretty printer lacks the flexibility required for common formatting options. This project addresses these issues by enhancing the AST/IR to preserve comments and adapting the pretty printer to support customizable formatting rules, ultimately creating a functional P4 code formatter for the first time. ...