P4C
The P4 Compiler
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jbay/instruction.cpp
1
17
18/* JBay overloads for instructions #included in instruction.cpp
19 * WARNING -- this is included in an anonymous namespace, as VLIWInstruction is
20 * in that anonymous namespace */
21
22template <typename REGS>
23void VLIWInstruction::write_regs_2(REGS &regs, Table *tbl, Table::Actions::Action *act) {
24 if (act != tbl->stage->imem_addr_use[imem_thread(tbl->gress)][act->addr]) {
25 LOG3("skipping " << tbl->name() << '.' << act->name << " as its imem is used by "
26 << tbl->stage->imem_addr_use[imem_thread(tbl->gress)][act->addr]->name);
27 return;
28 }
29 LOG2(this);
30 auto &imem = regs.dp.imem;
31 int iaddr = act->addr / ACTION_IMEM_COLORS;
32 int color = act->addr % ACTION_IMEM_COLORS;
33 unsigned bits = encode();
34 BUG_CHECK(slot >= 0, "slots must be >= 0");
35 unsigned off = slot % Phv::mau_groupsize();
36 unsigned side = 0, group = 0;
37 switch (slot / Phv::mau_groupsize()) {
38 case 0:
39 side = 0;
40 group = 0;
41 break;
42 case 1:
43 side = 0;
44 group = 1;
45 break;
46 case 2:
47 side = 1;
48 group = 0;
49 break;
50 case 3:
51 side = 1;
52 group = 1;
53 break;
54 case 4:
55 side = 0;
56 group = 0;
57 break;
58 case 5:
59 side = 0;
60 group = 1;
61 break;
62 case 6:
63 side = 1;
64 group = 0;
65 break;
66 case 7:
67 side = 1;
68 group = 1;
69 break;
70 case 8:
71 side = 0;
72 group = 0;
73 break;
74 case 9:
75 side = 0;
76 group = 1;
77 break;
78 case 10:
79 side = 0;
80 group = 2;
81 break;
82 case 11:
83 side = 1;
84 group = 0;
85 break;
86 case 12:
87 side = 1;
88 group = 1;
89 break;
90 case 13:
91 side = 1;
92 group = 2;
93 break;
94 default:
95 BUG("bad slot size %d", slot / Phv::mau_groupsize());
96 }
97
98 switch (Phv::reg(slot)->type) {
99 case Phv::Register::NORMAL:
100 switch (Phv::reg(slot)->size) {
101 case 8:
102 BUG_CHECK(group == 0 || group == 1, "bad group");
103 imem.imem_subword8[side][group][off][iaddr].imem_subword8_instr = bits;
104 imem.imem_subword8[side][group][off][iaddr].imem_subword8_color = color;
105 imem.imem_subword8[side][group][off][iaddr].imem_subword8_parity =
106 parity(bits) ^ color;
107 break;
108 case 16:
109 imem.imem_subword16[side][group][off][iaddr].imem_subword16_instr = bits;
110 imem.imem_subword16[side][group][off][iaddr].imem_subword16_color = color;
111 imem.imem_subword16[side][group][off][iaddr].imem_subword16_parity =
112 parity(bits) ^ color;
113 break;
114 case 32:
115 BUG_CHECK(group == 0 || group == 1, "bad group");
116 imem.imem_subword32[side][group][off][iaddr].imem_subword32_instr = bits;
117 imem.imem_subword32[side][group][off][iaddr].imem_subword32_color = color;
118 imem.imem_subword32[side][group][off][iaddr].imem_subword32_parity =
119 parity(bits) ^ color;
120 break;
121 default:
122 BUG("bad size %d", Phv::reg(slot)->size);
123 }
124 break;
125 case Phv::Register::MOCHA:
126 switch (Phv::reg(slot)->size) {
127 case 8:
128 BUG_CHECK(group == 0 || group == 1, "bad group");
129 imem.imem_mocha_subword8[side][group][off - 12][iaddr]
130 .imem_mocha_subword_instr = bits;
131 imem.imem_mocha_subword8[side][group][off - 12][iaddr]
132 .imem_mocha_subword_color = color;
133 imem.imem_mocha_subword8[side][group][off - 12][iaddr]
134 .imem_mocha_subword_parity = parity(bits) ^ color;
135 break;
136 case 16:
137 imem.imem_mocha_subword16[side][group][off - 12][iaddr]
138 .imem_mocha_subword_instr = bits;
139 imem.imem_mocha_subword16[side][group][off - 12][iaddr]
140 .imem_mocha_subword_color = color;
141 imem.imem_mocha_subword16[side][group][off - 12][iaddr]
142 .imem_mocha_subword_parity = parity(bits) ^ color;
143 break;
144 case 32:
145 BUG_CHECK(group == 0 || group == 1, "bad group");
146 imem.imem_mocha_subword32[side][group][off - 12][iaddr]
147 .imem_mocha_subword_instr = bits;
148 imem.imem_mocha_subword32[side][group][off - 12][iaddr]
149 .imem_mocha_subword_color = color;
150 imem.imem_mocha_subword32[side][group][off - 12][iaddr]
151 .imem_mocha_subword_parity = parity(bits) ^ color;
152 break;
153 default:
154 BUG("bad size %d", Phv::reg(slot)->size);
155 }
156 break;
157 case Phv::Register::DARK:
158 switch (Phv::reg(slot)->size) {
159 case 8:
160 BUG_CHECK(group == 0 || group == 1, "bad group");
161 imem.imem_dark_subword8[side][group][off - 16][iaddr].imem_dark_subword_instr =
162 bits;
163 imem.imem_dark_subword8[side][group][off - 16][iaddr].imem_dark_subword_color =
164 color;
165 imem.imem_dark_subword8[side][group][off - 16][iaddr].imem_dark_subword_parity =
166 parity(bits) ^ color;
167 break;
168 case 16:
169 imem.imem_dark_subword16[side][group][off - 16][iaddr].imem_dark_subword_instr =
170 bits;
171 imem.imem_dark_subword16[side][group][off - 16][iaddr].imem_dark_subword_color =
172 color;
173 imem.imem_dark_subword16[side][group][off - 16][iaddr]
174 .imem_dark_subword_parity = parity(bits) ^ color;
175 break;
176 case 32:
177 BUG_CHECK(group == 0 || group == 1, "bad group");
178 imem.imem_dark_subword32[side][group][off - 16][iaddr].imem_dark_subword_instr =
179 bits;
180 imem.imem_dark_subword32[side][group][off - 16][iaddr].imem_dark_subword_color =
181 color;
182 imem.imem_dark_subword32[side][group][off - 16][iaddr]
183 .imem_dark_subword_parity = parity(bits) ^ color;
184 break;
185 default:
186 BUG("bad size %d", Phv::reg(slot)->size);
187 }
188 break;
189 default:
190 BUG("bad type %d", Phv::reg(slot)->type);
191 }
192
193 auto &power_ctl = regs.dp.actionmux_din_power_ctl;
194 phvRead([&](const Phv::Slice &sl) { set_power_ctl_reg(power_ctl, sl.reg.mau_id()); });
195}
196
197void VLIWInstruction::write_regs(Target::JBay::mau_regs &regs, Table *tbl,
198 Table::Actions::Action *act) {
199 write_regs_2<Target::JBay::mau_regs>(regs, tbl, act);
200}
Phv::Slice
Definition bf-asm/phv.h:83
Table
Definition tables.h:98
Table::Actions::Action
Definition tables.h:538
VLIW::VLIWInstruction::write_regs_2
void write_regs_2(REGS &regs, Table *tbl, Table::Actions::Action *act)
Definition instruction.cpp:24