mau_power.h

 
#ifndef BF_P4C_MAU_MAU_POWER_H_
#define BF_P4C_MAU_MAU_POWER_H_
 
#include <fstream>
#include <map>
#include <ostream>
#include <string>
#include <vector>
 
#include "backends/tofino/bf-p4c/device.h"
#include "ir/ir.h"
#include "ir/unique_id.h"
#include "lib/dyn_vector.h"
#include "power_schema.h"
 
namespace MauPower {
 
using namespace P4;
 
enum mau_dep_t { DEP_CONCURRENT = 0, DEP_ACTION = 1, DEP_MATCH = 2 };
enum stage_feature_t {
    HAS_EXACT = 0,
    HAS_TCAM = 1,
    HAS_STATS = 2,
    HAS_SEL = 3,
    HAS_LPF_OR_WRED = 4,
    HAS_STFUL = 5,
    WIDE_SEL = 6
};
enum lut_t { NEXT_TABLE_LUT = 0, GLOB_EXEC_LUT = 1, LONG_BRANCH_LUT = 2 };
 
std::ostream &operator<<(std::ostream &, mau_dep_t);
// The internal encoding of stage numbers is:
//      0 to n-1 for ingress stages
//      n to 2n-1 for egress stages
//      2n to 3n-1 for ghost stages
// However, note that function signatures assume the stage argument
// runs from 0 to n-1.  This is checked.
std::string float2str(double d);
 
class MauFeatures {
 public:
    static const int kNumberGress = GRESS_T_COUNT;
    using PowerLogging = Logging::Power_Schema_Logger;
    // For calculating latencies
    // map from gress and stage number to Boolean indicating if resource type is in use.
    bitvec has_exact_[kNumberGress];
    // has_tcam_ would also include ternary result buses in ram array.
    bitvec has_tcam_[kNumberGress];
    bitvec has_meter_lpf_or_wred_[kNumberGress];
    bitvec has_selector_[kNumberGress];
    dyn_vector<int> max_selector_words_[kNumberGress];  // max across tables in stage
    bitvec has_stateful_[kNumberGress];
    bitvec has_stats_[kNumberGress];
 
    // map from UniqueId to Boolean indicating
    // if it will run at EOP.
    // The UniqueId is the attached table's UniqueId.
    std::map<UniqueId, bool> counter_runs_at_eop_;
    std::map<UniqueId, bool> meter_runs_at_eop_;
    // for keeping track if have LPF or WRED 'meter'
    std::map<UniqueId, bool> meter_is_lpf_or_wred_;
    // stores maximum number of selector members
    // (more than 120 requires multiple RAM words)
    std::map<UniqueId, int> selector_group_size_;
 
    // Maps stage number to vector of logical tables found in the stage
    dyn_vector<std::vector<const IR::MAU::Table *>> stage_to_tables_[kNumberGress];
    // Maps UniqueId to stage number it's in.
    std::map<UniqueId, int> table_to_stage_;
    // Maps UniqueId back to the table
    std::map<UniqueId, const IR::MAU::Table *> uid_to_table_;
 
 private:
    // Maps stage number to its dependency type to previous stage.
    // Note the encoding is as described above.
    std::map<int, mau_dep_t> stage_dep_to_previous_[kNumberGress];
 
 public:
    bool stage_has_feature(gress_t gress, int stage, stage_feature_t feature) const;
    int get_max_selector_words(gress_t gress, int stage) const;
    mau_dep_t get_dependency_for_gress_stage(gress_t g, int stage) const;
    void set_dependency_for_gress_stage(gress_t g, int stage, mau_dep_t dep);
    bool try_convert_to_match_dep();
    void update_deps_for_device();
 
    int compute_pipe_latency(gress_t gress) const;
    int compute_stage_latency(gress_t gress, int stage) const;
    int compute_pred_cycle(gress_t gress, int stage) const;
    bool stage_has_chained_feature(gress_t gress, int stage, stage_feature_t feature) const;
    void print_features(std::ostream &out, gress_t gress) const;
    void print_latency(std::ostream &out, gress_t gress) const;
    void log_json_stage_characteristics(gress_t g, PowerLogging *logger) const;
    std::ostream &emit_dep_asm(std::ostream &out, gress_t g, int stage) const;
    bool requires_dep_asm(gress_t g, int stage) const;
    bool are_there_more_tables(gress_t gress, int start_stage) const;
};
 
class MprSettings {
 public:
    const gress_t gress_;
    MauFeatures &mau_features_;
    MprSettings(gress_t gress, MauFeatures &);
    void set_mpr_stage(int stage, int mpr_stage);
    int get_mpr_stage(int stage) const;
    void set_mpr_next_table(int stage, int logical_id, int id_vector);
    void set_or_mpr_next_table(int stage, int logical_id, int id_vector);
    int get_mpr_next_table(int stage, int logical_id) const;
    void set_mpr_global_exec(int stage, int exec_bit, int id_vector);
    void set_or_mpr_global_exec(int stage, int exec_bit, int id_vector);
    int get_mpr_global_exec(int stage, int exec_bit) const;
    void set_mpr_long_branch(int stage, int tag_id, int id_vector);
    int get_mpr_long_branch(int stage, int tag_id) const;
    void set_or_mpr_long_branch(int stage, int tag_id, int id_vector);
    void set_mpr_always_run(int stage, int id_vector);
    void set_or_mpr_always_run(int stage, int id_vector);
    int get_mpr_always_run_for_stage(int stage) const;
    void set_mpr_bus_dep_glob_exec(int stage, int id_vector);
    void set_or_mpr_bus_dep_glob_exec(int stage, int id_vector);
    int get_mpr_bus_dep_glob_exec(int stage) const;
    void set_mpr_bus_dep_long_brch(int stage, int id_vector);
    void set_or_mpr_bus_dep_long_brch(int stage, int id_vector);
    int get_mpr_bus_dep_long_brch(int stage) const;
 
    friend std::ostream &operator<<(std::ostream &out, const MprSettings &m);
    bool need_to_emit(lut_t type, int stage) const;
    std::ostream &emit_stage_asm(std::ostream &out, int stage) const;
 
 private:
    dyn_vector<int> mpr_stage_id_;
 
    dyn_vector<dyn_vector<int>> mpr_next_table_;
 
    dyn_vector<dyn_vector<int>> mpr_global_exec_;
 
    dyn_vector<dyn_vector<int>> mpr_long_branch_;
 
    dyn_vector<int> mpr_always_run_;
 
    dyn_vector<int> mpr_bus_dep_glob_exec_;
 
    dyn_vector<int> mpr_bus_dep_long_brch_;
 
    void print_data(std::ostream &out, int cols, std::string id_name, std::vector<int> data,
                    bool use_bin) const;
 
 public:
    /* for each stage, which mpr_glob_exec bits output by this stage are needed by later stages.
     * for action dependent stages, this will be identical to the previous match dependent stage.
     */
    dyn_vector<int> glob_exec_use;
    /* for each stage, which mpr_long_branch tags output by this stage are needed by later stages.
     * for action dependent stages, this will be identical to the previous match dependent stage.
     */
    dyn_vector<int> long_branch_use;
};
 
/*
 * rams_read
 *    The total number of RAMs read.
 * rams_write
 *    The total number of RAMs written.  Only attached synth-2-port
 *    resources can write RAMs.
 * tcam_read
 *    The total number of TCAMs read.  Ternary tables have to read
 *    all TCAMs.
 * map_rams_read
 *    The total number of MapRAMs read.  MapRAMs are read by synth-2-port,
 *    idletime, and meter color.
 * map_rams_write
 *    The total number of MapRAMs written.  MapRAMs are written by
 *    synth-2-port, idletime, and meter color.
 * deferred_rams_read
 *    The total number of deferred RAMs read.  Deferred RAMs are read
 *    by meters and counters that run at EOP time.
 * deferred_rams_write
 *    The total number of DeferredRAMs written.  Deferred RAMs are written
 *    by meters and counters that run at EOP time.
 */
struct PowerMemoryAccess {
    using PowerLogging = Logging::Power_Schema_Logger;
    int ram_read = 0;
    int ram_write = 0;
    int tcam_read = 0;
    int map_ram_read = 0;
    int map_ram_write = 0;
    int deferred_ram_read = 0;
    int deferred_ram_write = 0;
 
    PowerMemoryAccess()
        : ram_read(0),
          ram_write(0),
          tcam_read(0),
          map_ram_read(0),
          map_ram_write(0),
          deferred_ram_read(0),
          deferred_ram_write(0) {}
 
    explicit PowerMemoryAccess(int ram_read, int ram_write, int tcam_read, int map_ram_read,
                               int map_ram_write, int deferred_ram_read, int deferred_ram_write)
        : ram_read(ram_read),
          ram_write(ram_write),
          tcam_read(tcam_read),
          map_ram_read(map_ram_read),
          map_ram_write(map_ram_write),
          deferred_ram_read(deferred_ram_read),
          deferred_ram_write(deferred_ram_write) {}
 
    friend std::ostream &operator<<(std::ostream &out, const PowerMemoryAccess &p) {
        out << "Memory access:" << std::endl;
        out << "   RAMs read " << p.ram_read << std::endl;
        out << "   RAMs write " << p.ram_write << std::endl;
        out << "   TCAMs read " << p.tcam_read << std::endl;
        out << "   MapRAMs read " << p.map_ram_read << std::endl;
        out << "   MapRAMs write " << p.map_ram_write << std::endl;
        out << "   Deferred RAMs read " << p.deferred_ram_read << std::endl;
        out << "   Deferred RAMs write " << p.deferred_ram_write << std::endl;
        return out;
    }
 
    PowerMemoryAccess &operator+=(const PowerMemoryAccess &p) {
        ram_read += p.ram_read;
        ram_write += p.ram_write;
        tcam_read += p.tcam_read;
        map_ram_read += p.map_ram_read;
        map_ram_write += p.map_ram_write;
        deferred_ram_read += p.deferred_ram_read;
        deferred_ram_write += p.deferred_ram_write;
        return *this;
    }
 
    PowerMemoryAccess operator+(const PowerMemoryAccess &p) const {
        PowerMemoryAccess rv = *this;
        rv += p;
        return rv;
    }
 
    double compute_table_power(int num_pipes) const;
 
    double compute_table_weight(double computed_power, int num_pipes) const;
    // Sets up JSON logging information.
    void log_json_memories(PowerLogging::StageDetails *) const;
};
 
}  // end namespace MauPower
 
#endif /* BF_P4C_MAU_MAU_POWER_H_ */