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tofino/bf-asm/target.h
1
17
18#ifndef BACKENDS_TOFINO_BF_ASM_TARGET_H_
19#define BACKENDS_TOFINO_BF_ASM_TARGET_H_
20
21#include "asm-types.h"
22#include "backends/tofino/bf-asm/config.h"
23#include "bfas.h"
24#include "lib/exceptions.h"
25#include "map.h"
26
27struct MemUnit;
28
35// TODO: clang-format adds space in __VA_OPT__
36#define FOR_ALL_TARGETS(M, ...) \
37 M(Tofino __VA_OPT__(,) __VA_ARGS__) \
38 M(JBay __VA_OPT__(,) __VA_ARGS__) \
39 M(Tofino2H __VA_OPT__(,) __VA_ARGS__) \
40 M(Tofino2M __VA_OPT__(,) __VA_ARGS__) \
41 M(Tofino2U __VA_OPT__(,) __VA_ARGS__) \
42 M(Tofino2A0 __VA_OPT__(,) __VA_ARGS__)
43#define FOR_ALL_REGISTER_SETS(M, ...) \
44 M(Tofino __VA_OPT__(,) __VA_ARGS__) \
45 M(JBay __VA_OPT__(,) __VA_ARGS__)
46#define FOR_ALL_TARGET_CLASSES(M, ...) M(Tofino __VA_OPT__(,) __VA_ARGS__)
47
48// alias FOR_ALL -> FOR_EACH so the the group name does need to be plural
49#define FOR_EACH_TARGET FOR_ALL_TARGETS
50#define FOR_EACH_REGISTER_SET FOR_ALL_REGISTER_SETS
51#define FOR_EACH_TARGET_CLASS FOR_ALL_TARGET_CLASSES
52
53#define TARGETS_IN_CLASS_Tofino(M, ...) \
54 M(Tofino __VA_OPT__(,) __VA_ARGS__) \
55 M(JBay __VA_OPT__(,) __VA_ARGS__) \
56 M(Tofino2H __VA_OPT__(,) __VA_ARGS__) \
57 M(Tofino2M __VA_OPT__(,) __VA_ARGS__) \
58 M(Tofino2U __VA_OPT__(,) __VA_ARGS__) \
59 M(Tofino2A0 __VA_OPT__(,) __VA_ARGS__)
60#define REGSETS_IN_CLASS_Tofino(M, ...) \
61 M(Tofino __VA_OPT__(,) __VA_ARGS__) \
62 M(JBay __VA_OPT__(,) __VA_ARGS__)
63
64#define TARGETS_USING_REGS_JBay(M, ...) \
65 M(JBay __VA_OPT__(,) __VA_ARGS__) \
66 M(Tofino2H __VA_OPT__(,) __VA_ARGS__) \
67 M(Tofino2M __VA_OPT__(,) __VA_ARGS__) \
68 M(Tofino2U __VA_OPT__(,) __VA_ARGS__) \
69 M(Tofino2A0 __VA_OPT__(,) __VA_ARGS__)
70#define TARGETS_USING_REGS_Tofino(M, ...) M(Tofino __VA_OPT__(,) __VA_ARGS__)
71
72#define TARGETS_IN_CLASS(CL, ...) TARGETS_IN_CLASS_##CL(__VA_ARGS__)
73#define TARGETS_USING_REGS(CL, ...) TARGETS_USING_REGS_##CL(__VA_ARGS__)
74#define REGSETS_IN_CLASS(CL, ...) REGSETS_IN_CLASS_##CL(__VA_ARGS__)
75
76#define INSTANTIATE_TARGET_TEMPLATE(TARGET, FUNC, ...) template FUNC(Target::TARGET::__VA_ARGS__);
77#define DECLARE_TARGET_CLASS(TARGET, ...) class TARGET __VA_ARGS__;
78#define FRIEND_TARGET_CLASS(TARGET, ...) friend class Target::TARGET __VA_ARGS__;
79
80#define PER_TARGET_CONSTANTS(M) \
81 M(const char *, name) \
82 M(target_t, register_set) \
83 M(int, ARAM_UNITS_PER_STAGE) \
84 M(int, DEPARSER_CHECKSUM_UNITS) \
85 M(int, DEPARSER_CONSTANTS) \
86 M(int, DEPARSER_MAX_FD_ENTRIES) \
87 M(int, DEPARSER_MAX_POV_BYTES) \
88 M(int, DEPARSER_MAX_POV_PER_USE) \
89 M(int, DP_UNITS_PER_STAGE) \
90 M(int, DYNAMIC_CONFIG) \
91 M(int, DYNAMIC_CONFIG_INPUT_BITS) \
92 M(bool, EGRESS_SEPARATE) \
93 M(int, END_OF_PIPE) \
94 M(int, EXACT_HASH_GROUPS) \
95 M(int, EXACT_HASH_TABLES) \
96 M(int, EXTEND_ALU_8_SLOTS) \
97 M(int, EXTEND_ALU_16_SLOTS) \
98 M(int, EXTEND_ALU_32_SLOTS) \
99 M(bool, GATEWAY_INHIBIT_INDEX) \
100 M(int, GATEWAY_MATCH_BITS) \
101 M(bool, GATEWAY_NEEDS_SEARCH_BUS) \
102 M(int, GATEWAY_PAYLOAD_GROUPS) \
103 M(int, GATEWAY_ROWS) \
104 M(bool, GATEWAY_SINGLE_XBAR_GROUP) \
105 M(bool, HAS_MPR) \
106 M(int, INSTR_SRC2_BITS) \
107 M(int, IMEM_COLORS) \
108 M(int, IXBAR_HASH_GROUPS) \
109 M(int, IXBAR_HASH_INDEX_MAX) \
110 M(int, IXBAR_HASH_INDEX_STRIDE) \
111 M(int, LOCAL_TIND_UNITS) \
112 M(int, LONG_BRANCH_TAGS) \
113 M(int, MAX_IMMED_ACTION_DATA) \
114 M(int, MAX_OVERHEAD_OFFSET) \
115 M(int, MAX_OVERHEAD_OFFSET_NEXT) \
116 M(int, MATCH_BYTE_16BIT_PAIRS) \
117 M(int, MATCH_REQUIRES_PHYSID) \
118 M(int, MAU_BASE_DELAY) \
119 M(int, MAU_BASE_PREDICATION_DELAY) \
120 M(int, MAU_ERROR_DELAY_ADJUST) \
121 M(int, METER_ALU_GROUP_DATA_DELAY) \
122 M(int, MINIMUM_INSTR_CONSTANT) \
123 M(bool, NEXT_TABLE_EXEC_COMBINED) \
124 M(int, NEXT_TABLE_SUCCESSOR_TABLE_DEPTH) \
125 M(int, NUM_MAU_STAGES_PRIVATE) \
126 M(int, NUM_EGRESS_STAGES_PRIVATE) \
127 M(int, NUM_PARSERS) \
128 M(int, NUM_PIPES) \
129 M(bool, OUTPUT_STAGE_EXTENSION_PRIVATE) \
130 M(int, PARSER_CHECKSUM_UNITS) \
131 M(bool, PARSER_EXTRACT_BYTES) \
132 M(int, PARSER_DEPTH_MAX_BYTES_INGRESS) \
133 M(int, PARSER_DEPTH_MAX_BYTES_EGRESS) \
134 M(int, PARSER_DEPTH_MAX_BYTES_MULTITHREADED_EGRESS) \
135 M(int, PARSER_DEPTH_MIN_BYTES_INGRESS) \
136 M(int, PARSER_DEPTH_MIN_BYTES_EGRESS) \
137 M(int, PHASE0_FORMAT_WIDTH) \
138 M(bool, REQUIRE_TCAM_ID) \
139 M(int, SRAM_EGRESS_ROWS) \
140 M(bool, SRAM_GLOBAL_ACCESS) \
141 M(int, SRAM_HBUS_SECTIONS_PER_STAGE) \
142 M(int, SRAM_HBUSSES_PER_ROW) \
143 M(int, SRAM_INGRESS_ROWS) \
144 M(int, SRAM_LOGICAL_UNITS_PER_ROW) \
145 M(int, SRAM_LAMBS_PER_STAGE) \
146 M(int, SRAM_REMOVED_COLUMNS) \
147 M(int, SRAM_STRIDE_COLUMN) \
148 M(int, SRAM_STRIDE_ROW) \
149 M(int, SRAM_STRIDE_STAGE) \
150 M(int, SRAM_UNITS_PER_ROW) \
151 M(int, STATEFUL_ALU_ADDR_WIDTH) \
152 M(int, STATEFUL_ALU_CONST_MASK) \
153 M(int, STATEFUL_ALU_CONST_MAX) \
154 M(int, STATEFUL_ALU_CONST_MIN) \
155 M(int, STATEFUL_ALU_CONST_WIDTH) \
156 M(int, STATEFUL_CMP_ADDR_WIDTH) \
157 M(int, STATEFUL_CMP_CONST_MASK) \
158 M(int, STATEFUL_CMP_CONST_MAX) \
159 M(int, STATEFUL_CMP_CONST_MIN) \
160 M(int, STATEFUL_CMP_CONST_WIDTH) \
161 M(int, STATEFUL_CMP_UNITS) \
162 M(int, STATEFUL_OUTPUT_UNITS) \
163 M(int, STATEFUL_PRED_MASK) \
164 M(int, STATEFUL_REGFILE_CONST_WIDTH) \
165 M(int, STATEFUL_REGFILE_ROWS) \
166 M(int, STATEFUL_TMATCH_UNITS) \
167 M(bool, SUPPORT_ALWAYS_RUN) \
168 M(bool, SUPPORT_CONCURRENT_STAGE_DEP) \
169 M(bool, SUPPORT_OVERFLOW_BUS) \
170 M(bool, SUPPORT_SALU_FAST_CLEAR) \
171 M(bool, SUPPORT_TRUE_EOP) \
172 M(bool, SYNTH2PORT_NEED_MAPRAMS) \
173 M(bool, TCAM_EXTRA_NIBBLE) \
174 M(bool, TCAM_GLOBAL_ACCESS) \
175 M(int, TCAM_MATCH_BUSSES) \
176 M(int, TCAM_MEMORY_FULL_WIDTH) \
177 M(int, TCAM_ROWS) \
178 M(int, TCAM_UNITS_PER_ROW) \
179 M(int, TCAM_XBAR_GROUPS) \
180 M(bool, TABLES_REQUIRE_ROW)
181
182#define DECLARE_PER_TARGET_CONSTANT(TYPE, NAME) static TYPE NAME();
183
184#define TARGET_CLASS_SPECIFIC_CLASSES \
185 class ActionTable; \
186 class CounterTable; \
187 class ExactMatchTable; \
188 class GatewayTable; \
189 class MeterTable; \
190 class StatefulTable; \
191 class TernaryIndirectTable; \
192 class TernaryMatchTable;
193#define REGISTER_SET_SPECIFIC_CLASSES /* none */
194#define TARGET_SPECIFIC_CLASSES /* none */
195
196class Target {
197 public:
198 class Phv;
199 FOR_ALL_TARGETS(DECLARE_TARGET_CLASS)
200 PER_TARGET_CONSTANTS(DECLARE_PER_TARGET_CONSTANT)
201
202 static int encodeConst(int src);
203
204 static int NUM_MAU_STAGES() {
205 return numMauStagesOverride ? numMauStagesOverride : NUM_MAU_STAGES_PRIVATE();
206 }
207 static int NUM_EGRESS_STAGES() {
208 int egress_stages = NUM_EGRESS_STAGES_PRIVATE();
209 return numMauStagesOverride && numMauStagesOverride < egress_stages ? numMauStagesOverride
210 : egress_stages;
211 }
212 static int NUM_STAGES(gress_t gr) {
213 return gr == EGRESS ? NUM_EGRESS_STAGES() : NUM_MAU_STAGES();
214 }
215
216 static int OUTPUT_STAGE_EXTENSION() {
217 return numMauStagesOverride ? 1 : OUTPUT_STAGE_EXTENSION_PRIVATE();
218 }
219
220 static void OVERRIDE_NUM_MAU_STAGES(int num);
221
222 static int SRAM_ROWS(gress_t gr) {
223 return gr == EGRESS ? SRAM_EGRESS_ROWS() : SRAM_INGRESS_ROWS();
224 }
225
226 // FIXME -- bus_type here is a Table::Layout::bus_type_t, but can't forward
227 // declare a nested type.
228 virtual int NUM_BUS_OF_TYPE_v(int bus_type) const;
229 static int NUM_BUS_OF_TYPE(int bus_type);
230
231 private:
232 static int numMauStagesOverride;
233};
234
235#include "backends/tofino/bf-asm/gen/tofino/memories.pipe_addrmap.h"
236#include "backends/tofino/bf-asm/gen/tofino/memories.pipe_top_level.h"
237#include "backends/tofino/bf-asm/gen/tofino/memories.prsr_mem_main_rspec.h"
238#include "backends/tofino/bf-asm/gen/tofino/regs.dprsr_hdr.h"
239#include "backends/tofino/bf-asm/gen/tofino/regs.dprsr_inp.h"
240#include "backends/tofino/bf-asm/gen/tofino/regs.ebp_rspec.h"
241#include "backends/tofino/bf-asm/gen/tofino/regs.ibp_rspec.h"
242#include "backends/tofino/bf-asm/gen/tofino/regs.mau_addrmap.h"
243#include "backends/tofino/bf-asm/gen/tofino/regs.pipe_addrmap.h"
244#include "backends/tofino/bf-asm/gen/tofino/regs.prsr_reg_merge_rspec.h"
245#include "backends/tofino/bf-asm/gen/tofino/regs.tofino.h"
246
247class Target::Tofino : public Target {
248 public:
249 static constexpr const char *const name = "tofino";
250 static constexpr target_t tag = TOFINO;
251 static constexpr target_t register_set = TOFINO;
252 typedef Target::Tofino target_type;
253 typedef Target::Tofino register_type;
254 class Phv;
255 struct top_level_regs {
256 typedef ::Tofino::memories_top _mem_top;
257 typedef ::Tofino::memories_pipe _mem_pipe;
258 typedef ::Tofino::regs_top _regs_top;
259 typedef ::Tofino::regs_pipe _regs_pipe;
260
261 ::Tofino::memories_top mem_top;
262 ::Tofino::memories_pipe mem_pipe;
263 ::Tofino::regs_top reg_top;
264 ::Tofino::regs_pipe reg_pipe;
265
266 // map from handle to parser regs
267 std::map<unsigned, ::Tofino::memories_all_parser_ *> parser_memory[2];
268 std::map<unsigned, ::Tofino::regs_all_parser_ingress *> parser_ingress;
269 std::map<unsigned, ::Tofino::regs_all_parser_egress *> parser_egress;
270 ::Tofino::regs_all_parse_merge parser_merge;
271 };
272 struct parser_regs : public ParserRegisterSet {
273 typedef ::Tofino::memories_all_parser_ _memory;
274 typedef ::Tofino::regs_all_parser_ingress _ingress;
275 typedef ::Tofino::regs_all_parser_egress _egress;
276 typedef ::Tofino::regs_all_parse_merge _merge;
277
278 ::Tofino::memories_all_parser_ memory[2];
279 ::Tofino::regs_all_parser_ingress ingress;
280 ::Tofino::regs_all_parser_egress egress;
281 ::Tofino::regs_all_parse_merge merge;
282 };
283
284 typedef ::Tofino::regs_match_action_stage_ mau_regs;
285 struct deparser_regs {
286 typedef ::Tofino::regs_all_deparser_input_phase _input;
287 typedef ::Tofino::regs_all_deparser_header_phase _header;
288
289 ::Tofino::regs_all_deparser_input_phase input;
290 ::Tofino::regs_all_deparser_header_phase header;
291 };
292 enum {
293 ARAM_UNITS_PER_STAGE = 0,
294 PARSER_CHECKSUM_UNITS = 2,
295 PARSER_EXTRACT_BYTES = false,
296 PARSER_DEPTH_MAX_BYTES_INGRESS = (((1 << 10) - 1) * 16),
297 PARSER_DEPTH_MAX_BYTES_EGRESS = (((1 << 10) - 1) * 16),
298 PARSER_DEPTH_MAX_BYTES_MULTITHREADED_EGRESS = 160,
299 PARSER_DEPTH_MIN_BYTES_INGRESS = 0,
300 PARSER_DEPTH_MIN_BYTES_EGRESS = 65,
301 MATCH_BYTE_16BIT_PAIRS = true,
302 MATCH_REQUIRES_PHYSID = false,
303 MAX_IMMED_ACTION_DATA = 32,
304 MAX_OVERHEAD_OFFSET = 64,
305 MAX_OVERHEAD_OFFSET_NEXT = 40,
306 NUM_MAU_STAGES_PRIVATE = 12,
307 NUM_EGRESS_STAGES_PRIVATE = NUM_MAU_STAGES_PRIVATE,
308 ACTION_INSTRUCTION_MAP_WIDTH = 7,
309 DEPARSER_CHECKSUM_UNITS = 6,
310 DEPARSER_CONSTANTS = 0,
311 DEPARSER_MAX_POV_BYTES = 32,
312 DEPARSER_MAX_POV_PER_USE = 1,
313 DEPARSER_MAX_FD_ENTRIES = 192,
314 DP_UNITS_PER_STAGE = 0,
315 DYNAMIC_CONFIG = 0,
316 DYNAMIC_CONFIG_INPUT_BITS = 0,
317 EGRESS_SEPARATE = false,
318 END_OF_PIPE = 0xff,
319 EXACT_HASH_GROUPS = 8,
320 EXACT_HASH_TABLES = 16,
321 EXTEND_ALU_8_SLOTS = 0,
322 EXTEND_ALU_16_SLOTS = 0,
323 EXTEND_ALU_32_SLOTS = 0,
324 GATEWAY_INHIBIT_INDEX = false,
325 GATEWAY_MATCH_BITS = 56, // includes extra expansion for range match
326 GATEWAY_NEEDS_SEARCH_BUS = true,
327 GATEWAY_PAYLOAD_GROUPS = 1,
328 GATEWAY_ROWS = 8,
329 GATEWAY_SINGLE_XBAR_GROUP = true,
330 SUPPORT_TRUE_EOP = 0,
331 INSTR_SRC2_BITS = 4,
332 IMEM_COLORS = 2,
333 IXBAR_HASH_GROUPS = 8,
334 IXBAR_HASH_INDEX_MAX = 40,
335 IXBAR_HASH_INDEX_STRIDE = 10,
336 LOCAL_TIND_UNITS = 0,
337 LONG_BRANCH_TAGS = 0,
338 MAU_BASE_DELAY = 20,
339 MAU_BASE_PREDICATION_DELAY = 11,
340 MAU_ERROR_DELAY_ADJUST = 2,
341 METER_ALU_GROUP_DATA_DELAY = 13,
342 // To avoid under run scenarios, there is a minimum egress pipeline latency required
343 MINIMUM_REQUIRED_EGRESS_PIPELINE_LATENCY = 160,
344 NEXT_TABLE_EXEC_COMBINED = false, // no next_exec on tofino1 at all
345 NEXT_TABLE_SUCCESSOR_TABLE_DEPTH = 8,
346 PHASE0_FORMAT_WIDTH = 64,
347 REQUIRE_TCAM_ID = false, // miss-only tables do not need a tcam id
348 SRAM_EGRESS_ROWS = 8,
349 SRAM_GLOBAL_ACCESS = false,
350 SRAM_HBUS_SECTIONS_PER_STAGE = 0,
351 SRAM_HBUSSES_PER_ROW = 0,
352 SRAM_INGRESS_ROWS = 8,
353 SRAM_LAMBS_PER_STAGE = 0,
354 SRAM_LOGICAL_UNITS_PER_ROW = 6,
355 SRAM_REMOVED_COLUMNS = 2,
356 SRAM_STRIDE_COLUMN = 1,
357 SRAM_STRIDE_ROW = 12,
358 SRAM_STRIDE_STAGE = 0,
359 SRAM_UNITS_PER_ROW = 12,
360 STATEFUL_CMP_UNITS = 2,
361 STATEFUL_CMP_ADDR_WIDTH = 2,
362 STATEFUL_CMP_CONST_WIDTH = 4,
363 STATEFUL_CMP_CONST_MASK = 0xf,
364 STATEFUL_CMP_CONST_MIN = -8,
365 STATEFUL_CMP_CONST_MAX = 7,
366 STATEFUL_TMATCH_UNITS = 0,
367 STATEFUL_OUTPUT_UNITS = 1,
368 STATEFUL_PRED_MASK = (1U << (1 << STATEFUL_CMP_UNITS)) - 1,
369 STATEFUL_REGFILE_ROWS = 4,
370 STATEFUL_REGFILE_CONST_WIDTH = 32,
371 SUPPORT_ALWAYS_RUN = 0,
372 HAS_MPR = 0,
373 SUPPORT_CONCURRENT_STAGE_DEP = 1,
374 SUPPORT_OVERFLOW_BUS = 1,
375 SUPPORT_SALU_FAST_CLEAR = 0,
376 STATEFUL_ALU_ADDR_WIDTH = 2,
377 STATEFUL_ALU_CONST_WIDTH = 4,
378 STATEFUL_ALU_CONST_MASK = 0xf,
379 STATEFUL_ALU_CONST_MIN = -8, // TODO Is the same as the following one?
380 STATEFUL_ALU_CONST_MAX = 7,
381 MINIMUM_INSTR_CONSTANT = -8, // TODO
382 NUM_PARSERS = 18,
383 NUM_PIPES = 4,
384 OUTPUT_STAGE_EXTENSION_PRIVATE = 0,
385 SYNTH2PORT_NEED_MAPRAMS = true,
386 TCAM_EXTRA_NIBBLE = true,
387 TCAM_GLOBAL_ACCESS = false,
388 TCAM_MATCH_BUSSES = 2,
389 TCAM_MEMORY_FULL_WIDTH = 47,
390 TCAM_ROWS = 12,
391 TCAM_UNITS_PER_ROW = 2,
392 TCAM_XBAR_GROUPS = 12,
393 TABLES_REQUIRE_ROW = 1,
394 };
395 static int encodeConst(int src) { return (src >> 10 << 15) | (0x8 << 10) | (src & 0x3ff); }
396 TARGET_SPECIFIC_CLASSES
397 REGISTER_SET_SPECIFIC_CLASSES
398 TARGET_CLASS_SPECIFIC_CLASSES
399};
400
401void declare_registers(const Target::Tofino::top_level_regs *regs);
402void undeclare_registers(const Target::Tofino::top_level_regs *regs);
403void declare_registers(const Target::Tofino::parser_regs *regs);
404void undeclare_registers(const Target::Tofino::parser_regs *regs);
405void declare_registers(const Target::Tofino::mau_regs *regs, bool ignore, int stage);
406void declare_registers(const Target::Tofino::deparser_regs *regs);
407void undeclare_registers(const Target::Tofino::deparser_regs *regs);
408void emit_parser_registers(const Target::Tofino::top_level_regs *regs, std::ostream &);
409
410#include "backends/tofino/bf-asm/gen/jbay/memories.jbay_mem.h"
411#include "backends/tofino/bf-asm/gen/jbay/memories.pipe_addrmap.h"
412#include "backends/tofino/bf-asm/gen/jbay/memories.prsr_mem_main_rspec.h"
413#include "backends/tofino/bf-asm/gen/jbay/regs.dprsr_reg.h"
414#include "backends/tofino/bf-asm/gen/jbay/regs.epb_prsr4_reg.h"
415#include "backends/tofino/bf-asm/gen/jbay/regs.ipb_prsr4_reg.h"
416#include "backends/tofino/bf-asm/gen/jbay/regs.jbay_reg.h"
417#include "backends/tofino/bf-asm/gen/jbay/regs.mau_addrmap.h"
418#include "backends/tofino/bf-asm/gen/jbay/regs.pipe_addrmap.h"
419#include "backends/tofino/bf-asm/gen/jbay/regs.pmerge_reg.h"
420#include "backends/tofino/bf-asm/gen/jbay/regs.prsr_reg_main_rspec.h"
421
422class Target::JBay : public Target {
423 public:
424 static constexpr const char *const name = "tofino2";
425 static constexpr target_t tag = JBAY;
426 static constexpr target_t register_set = JBAY;
427 typedef Target::JBay target_type;
428 typedef Target::JBay register_type;
429 class Phv;
430 struct top_level_regs {
431 typedef ::JBay::memories_top _mem_top;
432 typedef ::JBay::memories_pipe _mem_pipe;
433 typedef ::JBay::regs_top _regs_top;
434 typedef ::JBay::regs_pipe _regs_pipe;
435
436 ::JBay::memories_top mem_top;
437 ::JBay::memories_pipe mem_pipe;
438 ::JBay::regs_top reg_top;
439 ::JBay::regs_pipe reg_pipe;
440
441 // map from handle to parser regs
442 std::map<unsigned, ::JBay::memories_parser_ *> parser_memory[2];
443 std::map<unsigned, ::JBay::regs_parser_ingress *> parser_ingress;
444 std::map<unsigned, ::JBay::regs_parser_egress *> parser_egress;
445 std::map<unsigned, ::JBay::regs_parser_main_ *> parser_main[2];
446 ::JBay::regs_parse_merge parser_merge;
447 };
448 struct parser_regs : public ParserRegisterSet {
449 typedef ::JBay::memories_parser_ _memory;
450 typedef ::JBay::regs_parser_ingress _ingress; // [9]
451 typedef ::JBay::regs_parser_egress _egress; // [9]
452 typedef ::JBay::regs_parser_main_ _main; // [9]
453 typedef ::JBay::regs_parse_merge _merge; // [1]
454
455 ::JBay::memories_parser_ memory[2];
456 ::JBay::regs_parser_ingress ingress;
457 ::JBay::regs_parser_egress egress;
458 ::JBay::regs_parser_main_ main[2];
459 ::JBay::regs_parse_merge merge;
460 };
461
462 typedef ::JBay::regs_match_action_stage_ mau_regs;
463 typedef ::JBay::regs_deparser deparser_regs;
464 enum : int {
465 ARAM_UNITS_PER_STAGE = 0,
466 PARSER_CHECKSUM_UNITS = 5,
467 PARSER_EXTRACT_BYTES = true,
468 PARSER_DEPTH_MAX_BYTES_INGRESS = (((1 << 10) - 1) * 16),
469 PARSER_DEPTH_MAX_BYTES_EGRESS = (32 * 16),
470 PARSER_DEPTH_MAX_BYTES_MULTITHREADED_EGRESS = (32 * 16),
471 PARSER_DEPTH_MIN_BYTES_INGRESS = 0,
472 PARSER_DEPTH_MIN_BYTES_EGRESS = 0,
473 MATCH_BYTE_16BIT_PAIRS = false,
474 MATCH_REQUIRES_PHYSID = false,
475 MAX_IMMED_ACTION_DATA = 32,
476 MAX_OVERHEAD_OFFSET = 64,
477 MAX_OVERHEAD_OFFSET_NEXT = 40,
478#ifdef EMU_OVERRIDE_STAGE_COUNT
479 NUM_MAU_STAGES_PRIVATE = EMU_OVERRIDE_STAGE_COUNT,
480 OUTPUT_STAGE_EXTENSION_PRIVATE = 1,
481#else
482 NUM_MAU_STAGES_PRIVATE = 20,
483 OUTPUT_STAGE_EXTENSION_PRIVATE = 0,
484#endif
485 NUM_EGRESS_STAGES_PRIVATE = NUM_MAU_STAGES_PRIVATE,
486 ACTION_INSTRUCTION_MAP_WIDTH = 8,
487 DEPARSER_CHECKSUM_UNITS = 8,
488 DEPARSER_CONSTANTS = 8,
489 DEPARSER_MAX_POV_BYTES = 16,
490 DEPARSER_MAX_POV_PER_USE = 1,
491 DEPARSER_CHUNKS_PER_GROUP = 8,
492 DEPARSER_CHUNK_SIZE = 8,
493 DEPARSER_CHUNK_GROUPS = 16,
494 DEPARSER_CLOTS_PER_GROUP = 4,
495 DEPARSER_TOTAL_CHUNKS = DEPARSER_CHUNK_GROUPS * DEPARSER_CHUNKS_PER_GROUP,
496 DEPARSER_MAX_FD_ENTRIES = DEPARSER_TOTAL_CHUNKS,
497 DP_UNITS_PER_STAGE = 0,
498 DYNAMIC_CONFIG = 0,
499 DYNAMIC_CONFIG_INPUT_BITS = 0,
500 EGRESS_SEPARATE = false,
501 END_OF_PIPE = 0x1ff,
502 EXACT_HASH_GROUPS = 8,
503 EXACT_HASH_TABLES = 16,
504 EXTEND_ALU_8_SLOTS = 0,
505 EXTEND_ALU_16_SLOTS = 0,
506 EXTEND_ALU_32_SLOTS = 0,
507 GATEWAY_INHIBIT_INDEX = false,
508 GATEWAY_MATCH_BITS = 56, // includes extra expansion for range match
509 GATEWAY_NEEDS_SEARCH_BUS = true,
510 GATEWAY_PAYLOAD_GROUPS = 5,
511 GATEWAY_ROWS = 8,
512 GATEWAY_SINGLE_XBAR_GROUP = true,
513 SUPPORT_TRUE_EOP = 1,
514 INSTR_SRC2_BITS = 5,
515 IMEM_COLORS = 2,
516 IXBAR_HASH_GROUPS = 8,
517 IXBAR_HASH_INDEX_MAX = 40,
518 IXBAR_HASH_INDEX_STRIDE = 10,
519 LOCAL_TIND_UNITS = 0,
520 LONG_BRANCH_TAGS = 8,
521 MAU_BASE_DELAY = 23,
522 MAU_BASE_PREDICATION_DELAY = 13,
523 MAU_ERROR_DELAY_ADJUST = 3,
524 METER_ALU_GROUP_DATA_DELAY = 15,
525 NEXT_TABLE_EXEC_COMBINED = true,
526 NEXT_TABLE_SUCCESSOR_TABLE_DEPTH = 8,
527 PHASE0_FORMAT_WIDTH = 128,
528 REQUIRE_TCAM_ID = false, // miss-only tables do not need a tcam id
529 SRAM_EGRESS_ROWS = 8,
530 SRAM_GLOBAL_ACCESS = false,
531 SRAM_HBUS_SECTIONS_PER_STAGE = 0,
532 SRAM_HBUSSES_PER_ROW = 0,
533 SRAM_INGRESS_ROWS = 8,
534 SRAM_LAMBS_PER_STAGE = 0,
535 SRAM_LOGICAL_UNITS_PER_ROW = 6,
536 SRAM_REMOVED_COLUMNS = 2,
537 SRAM_STRIDE_COLUMN = 1,
538 SRAM_STRIDE_ROW = 12,
539 SRAM_STRIDE_STAGE = 0,
540 SRAM_UNITS_PER_ROW = 12,
541 STATEFUL_CMP_UNITS = 4,
542 STATEFUL_CMP_ADDR_WIDTH = 2,
543 STATEFUL_CMP_CONST_WIDTH = 6,
544 STATEFUL_CMP_CONST_MASK = 0x3f,
545 STATEFUL_CMP_CONST_MIN = -32,
546 STATEFUL_CMP_CONST_MAX = 31,
547 STATEFUL_TMATCH_UNITS = 2,
548 STATEFUL_OUTPUT_UNITS = 4,
549 STATEFUL_PRED_MASK = (1U << (1 << STATEFUL_CMP_UNITS)) - 1,
550 STATEFUL_REGFILE_ROWS = 4,
551 STATEFUL_REGFILE_CONST_WIDTH = 34,
552 SUPPORT_ALWAYS_RUN = 1,
553 HAS_MPR = 1,
554 SUPPORT_CONCURRENT_STAGE_DEP = 0,
555 SUPPORT_OVERFLOW_BUS = 0,
556 SUPPORT_SALU_FAST_CLEAR = 1,
557 STATEFUL_ALU_ADDR_WIDTH = 2,
558 STATEFUL_ALU_CONST_WIDTH = 4,
559 STATEFUL_ALU_CONST_MASK = 0xf,
560 STATEFUL_ALU_CONST_MIN = -8, // TODO Is the same as the following one?
561 STATEFUL_ALU_CONST_MAX = 7,
562 MINIMUM_INSTR_CONSTANT = -4, // TODO
563 NUM_PARSERS = 36,
564 NUM_PIPES = 4,
565 TABLES_REQUIRE_ROW = 1,
566 SYNTH2PORT_NEED_MAPRAMS = true,
567 TCAM_EXTRA_NIBBLE = true,
568 TCAM_GLOBAL_ACCESS = false,
569 TCAM_MATCH_BUSSES = 2,
570 TCAM_MEMORY_FULL_WIDTH = 47,
571 TCAM_ROWS = 12,
572 TCAM_UNITS_PER_ROW = 2,
573 TCAM_XBAR_GROUPS = 12,
574 };
575 static int encodeConst(int src) { return (src >> 11 << 16) | (0x8 << 11) | (src & 0x7ff); }
576 TARGET_SPECIFIC_CLASSES
577 REGISTER_SET_SPECIFIC_CLASSES
578};
579void declare_registers(const Target::JBay::top_level_regs *regs);
580void undeclare_registers(const Target::JBay::top_level_regs *regs);
581void declare_registers(const Target::JBay::parser_regs *regs);
582void undeclare_registers(const Target::JBay::parser_regs *regs);
583void declare_registers(const Target::JBay::mau_regs *regs, bool ignore, int stage);
584void declare_registers(const Target::JBay::deparser_regs *regs);
585
586class Target::Tofino2H : public Target::JBay {
587 public:
588 static constexpr const char *const name = "tofino2h";
589 static constexpr target_t tag = TOFINO2H;
590 typedef Target::Tofino2H target_type;
591 class Phv;
592 enum {
593 NUM_MAU_STAGES_PRIVATE = 6,
594 NUM_EGRESS_STAGES_PRIVATE = NUM_MAU_STAGES_PRIVATE,
595 OUTPUT_STAGE_EXTENSION_PRIVATE = 1,
596 };
597 TARGET_SPECIFIC_CLASSES
598};
599
600class Target::Tofino2M : public Target::JBay {
601 public:
602 static constexpr const char *const name = "tofino2m";
603 static constexpr target_t tag = TOFINO2M;
604 typedef Target::Tofino2M target_type;
605 class Phv;
606 enum {
607 NUM_MAU_STAGES_PRIVATE = 12,
608 NUM_EGRESS_STAGES_PRIVATE = NUM_MAU_STAGES_PRIVATE,
609 OUTPUT_STAGE_EXTENSION_PRIVATE = 1,
610 };
611 TARGET_SPECIFIC_CLASSES
612};
613
614class Target::Tofino2U : public Target::JBay {
615 public:
616 static constexpr const char *const name = "tofino2u";
617 static constexpr target_t tag = TOFINO2U;
618 typedef Target::Tofino2U target_type;
619 class Phv;
620 enum {
621 NUM_MAU_STAGES_PRIVATE = 20,
622 NUM_EGRESS_STAGES_PRIVATE = NUM_MAU_STAGES_PRIVATE,
623 };
624 TARGET_SPECIFIC_CLASSES
625};
626
627class Target::Tofino2A0 : public Target::JBay {
628 public:
629 static constexpr const char *const name = "tofino2a0";
630 static constexpr target_t tag = TOFINO2A0;
631 typedef Target::Tofino2A0 target_type;
632 class Phv;
633 enum {
634 NUM_MAU_STAGES_PRIVATE = 20,
635 NUM_EGRESS_STAGES_PRIVATE = NUM_MAU_STAGES_PRIVATE,
636 };
637 TARGET_SPECIFIC_CLASSES
638};
639
640void emit_parser_registers(const Target::JBay::top_level_regs *regs, std::ostream &);
641
644#define SWITCH_FOREACH_TARGET(VAR, ...) \
645 switch (VAR) { \
646 FOR_ALL_TARGETS(DO_SWITCH_FOREACH_TARGET, __VA_ARGS__) \
647 default: \
648 BUG("invalid target"); \
649 }
650
651#define DO_SWITCH_FOREACH_TARGET(TARGET_, ...) \
652 case Target::TARGET_::tag: { \
653 typedef Target::TARGET_ TARGET; \
654 __VA_ARGS__ \
655 break; \
656 }
657
658#define SWITCH_FOREACH_REGISTER_SET(VAR, ...) \
659 switch (VAR) { \
660 FOR_ALL_REGISTER_SETS(DO_SWITCH_FOREACH_REGISTER_SET, __VA_ARGS__) \
661 default: \
662 BUG("invalid target"); \
663 }
664
665#define DO_SWITCH_FOREACH_REGISTER_SET(REGS_, ...) \
666 TARGETS_USING_REGS(REGS_, CASE_FOR_TARGET) { \
667 typedef Target::REGS_ TARGET; \
668 __VA_ARGS__ \
669 break; \
670 }
671
672#define SWITCH_FOREACH_TARGET_CLASS(VAR, ...) \
673 switch (VAR) { \
674 FOR_ALL_TARGET_CLASSES(DO_SWITCH_FOREACH_TARGET_CLASS, __VA_ARGS__) \
675 default: \
676 BUG("invalid target"); \
677 }
678
679#define DO_SWITCH_FOREACH_TARGET_CLASS(CLASS_, ...) \
680 TARGETS_IN_CLASS(CLASS_, CASE_FOR_TARGET) { \
681 typedef Target::CLASS_ TARGET; \
682 __VA_ARGS__ \
683 break; \
684 }
685
686#define CASE_FOR_TARGET(TARGET) case Target::TARGET::tag:
687
688/* macro to define a function that overloads over a GROUP of types -- will declare all the
689 * functions that overload on a Target::type argument and a 'generic' overload that calls
690 * the right specific overload based on options.target
691 * GROUP can be one of
692 * TARGET -- overload on all the different targets
693 * REGISTER_SET -- overload just on the register sets (targets that share a register
694 * set will only have one overload)
695 * TARGET_CLASS -- overload based on the CLASS
696 * RTYPE NAME ARGDECL together make the declaration of the (generic) function, the overloads
697 * will all have a Target::type argument prepended. The final ARGS argument is the argument
698 * list that that will be forwarded (basically ARGDECL without the types)
699 */
700#define EXPAND(...) __VA_ARGS__
701#define EXPAND_COMMA(...) __VA_OPT__(,) __VA_ARGS__
702#define EXPAND_COMMA_CLOSE(...) __VA_OPT__(,) __VA_ARGS__ )
703#define TARGET_OVERLOAD(TARGET, FN, ARGS, ...) FN(Target::TARGET::EXPAND ARGS) __VA_ARGS__;
704
705#define DECL_OVERLOAD_FUNC(TARGET, RTYPE, NAME, ARGDECL, ARGS) \
706 RTYPE NAME(Target::TARGET EXPAND_COMMA_CLOSE ARGDECL;
707#define OVERLOAD_FUNC_FOREACH(GROUP, RTYPE, NAME, ARGDECL, ARGS, ...) \
708 FOR_EACH_##GROUP(DECL_OVERLOAD_FUNC, RTYPE, NAME, ARGDECL, ARGS) \
709 RTYPE NAME ARGDECL __VA_ARGS__ { \
710 SWITCH_FOREACH_##GROUP(options.target, return NAME(TARGET() EXPAND_COMMA ARGS);) \
711 }
712
713#endif /* BACKENDS_TOFINO_BF_ASM_TARGET_H_ */
Target::JBay::Phv
Definition bf-asm/jbay/phv.h:23
Target::JBay::top_level_regs
Definition tofino/bf-asm/target.h:430
Target::Phv
Definition bf-asm/phv.h:315
Target::Tofino2A0::Phv
Definition bf-asm/jbay/phv.h:52
Target::Tofino2H::Phv
Definition bf-asm/jbay/phv.h:40
Target::Tofino2M::Phv
Definition bf-asm/jbay/phv.h:44
Target::Tofino2U::Phv
Definition bf-asm/jbay/phv.h:48
Target::Tofino::Phv
Definition bf-asm/tofino/phv.h:23
Target::Tofino::deparser_regs
Definition tofino/bf-asm/target.h:285
Target::Tofino::top_level_regs
Definition tofino/bf-asm/target.h:255
Target
Definition tofino/bf-asm/target.h:196
MemUnit
Definition tables.h:71
Target::JBay::parser_regs
Definition tofino/bf-asm/target.h:448
Target::Tofino::parser_regs
Definition tofino/bf-asm/target.h:272