Stage_data Class Reference

#include <stage.h>

Inheritance diagram for Stage_data:

Public Types
enum	{   USE_TCAM = 1 , USE_STATEFUL = 4 , USE_METER = 8 , USE_METER_LPF_RED = 16 ,   USE_SELECTOR = 32 , USE_WIDE_SELECTOR = 64 , USE_STATEFUL_DIVIDE = 128 }
enum	{ NONE = 0 , CONCURRENT = 1 , ACTION_DEP = 2 , MATCH_DEP = 3 }

Public Attributes
BFN::Alloc1D< Table *, ACTION_DATA_BUS_SLOTS >	action_bus_use
bitvec	action_bus_use_bit_mask
BFN::Alloc1D< Table *, LOGICAL_SRAM_ROWS >	action_data_use
bitvec	action_set [3]
BFN::Alloc1Dbase< ActionTable * >	action_unit_use
bitvec	action_use [3]
std::set< Stage ** >	all_refs
BFN::Alloc1Dbase< Synth2Port * >	dp_unit_use
ErrorMode	error_mode [2]
int	group_table_use [2]
BFN::Alloc2D< GatewayTable *, SRAM_ROWS, 2 >	gw_payload_use
BFN::Alloc2D< GatewayTable *, SRAM_ROWS, 2 >	gw_unit_use
BFN::Alloc1D< std::vector< HashDistribution * >, 6 >	hash_dist_use
BFN::Alloc1Dbase< std::vector< InputXbar * > >	hash_group_use
BFN::Alloc1Dbase< std::vector< InputXbar * > >	hash_table_use
BFN::Alloc1D< Table *, IDLETIME_BUSSES >	idletime_bus_use
BFN::Alloc2D< Table::Actions::Action *, 2, ACTION_IMEM_ADDR_MAX >	imem_addr_use
bitvec	imem_use [ACTION_IMEM_SLOTS]
ordered_map< InputXbar::Group, std::vector< InputXbar * > >	ixbar_use
BFN::Alloc1Dbase< Table * >	local_tind_use
BFN::Alloc1D< Table *, LOGICAL_TABLES_PER_STAGE >	logical_id_use
unsigned	long_branch_terminate = 0
unsigned	long_branch_thread [3] = {0}
BFN::Alloc1D< Table::NextTables *, MAX_LONGBRANCH_TAGS >	long_branch_use
BFN::Alloc2D< Table *, SRAM_ROWS, MAPRAM_UNITS_PER_ROW >	mapram_use
BFN::Alloc2D< Table *, SRAM_ROWS, 2 >	match_result_bus_use
bitvec	match_use [3]
BFN::Alloc1D< Table *, LOGICAL_SRAM_ROWS >	meter_bus_use
int	mpr_always_run = 0
int	mpr_bus_dep_glob_exec [3] = {0}
int	mpr_bus_dep_long_branch [3] = {0}
BFN::Alloc1D< int, LOGICAL_TABLES_PER_STAGE >	mpr_glob_exec_lut
BFN::Alloc1D< int, MAX_LONGBRANCH_TAGS >	mpr_long_brch_lut
BFN::Alloc2D< int, 3, LOGICAL_TABLES_PER_STAGE >	mpr_next_table_lut
int	mpr_stage_id [3] = {0}
BFN::Alloc1D< Table *, LOGICAL_SRAM_ROWS >	overflow_bus_use
int	pass1_logical_id = -1
int	pass1_tcam_id = -1
BFN::Alloc1D< Table *, PHYSICAL_TABLES_PER_STAGE >	physical_id_use
BFN::Alloc1D< Table *, LOGICAL_SRAM_ROWS >	selector_adr_bus_use
BFN::Alloc2D< Table *, SRAM_ROWS, 2 >	sram_search_bus_use
BFN::Alloc2Dbase< Table * >	sram_use
enum Stage_data:: { ... }	stage_dep [2]
int	stageno
BFN::Alloc1D< Table *, LOGICAL_SRAM_ROWS >	stats_bus_use
BFN::Alloc3Dbase< Table * >	stm_hbus_use
int	table_use [2]
std::vector< Table * >	tables
BFN::Alloc2D< std::pair< Table *, int >, TCAM_ROWS, 2 >	tcam_byte_group_use
BFN::Alloc1D< Table *, TCAM_TABLES_PER_STAGE >	tcam_id_use
BFN::Alloc2D< Table *, SRAM_ROWS, 2 >	tcam_indirect_bus_use
BFN::Alloc1D< Table *, TCAM_XBAR_INPUT_BYTES >	tcam_ixbar_input
BFN::Alloc2Dbase< Table * >	tcam_match_bus_use
BFN::Alloc2Dbase< Table * >	tcam_use

Static Public Attributes
static std::map< int, std::pair< bool, int > >	teop

Protected Member Functions
	Stage_data (const Stage_data &)=delete
	Stage_data (int stage, bool egress_only)
	Stage_data (Stage_data &&)=default

Detailed Description

Copyright (C) 2024 Intel Corporation

Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

SPDX-License-Identifier: Apache-2.0

Member Data Documentation

teop

std::map< int, std::pair< bool, int > > Stage_data::teop

static

Initial value:

= {
    {0, {false, INT_MAX}}, {1, {false, INT_MAX}}, {2, {false, INT_MAX}}, {3, {false, INT_MAX}}}