TableFormat::Use Struct Reference

Classes
struct	match_group_use
struct	TCAM_use

Public Member Functions
void	clear ()
bool	has_overhead () const
bool	instr_in_overhead () const
int	next_table_bits () const
bitvec	no_overhead_atcam_result_bus_words () const
bitvec	overhead () const
bitvec	result_bus_words () const

Public Attributes
bitvec	avail_sb_bytes
std::map< IXBar::Use::Byte, bitvec >	ghost_bits
bool	identity_hash = false
bitvec	immed_mask
std::map< int, safe_vector< int > >	ixbar_group_per_width
safe_vector< safe_vector< int > >	match_group_map
safe_vector< match_group_use >	match_groups
IR::MAU::PfeLocation	meter_pfe_loc = IR::MAU::PfeLocation::NOT_SET
IR::MAU::TypeLocation	meter_type_loc = IR::MAU::TypeLocation::NOT_SET
bool	only_one_result_bus = false
std::map< int, int >	payload_map
int	proxy_hash_group = -1
safe_vector< bool >	result_bus_needed
int	split_midbyte = -1
IR::MAU::PfeLocation	stats_pfe_loc = IR::MAU::PfeLocation::NOT_SET
safe_vector< TCAM_use >	tcam_use

Member Function Documentation

no_overhead_atcam_result_bus_words()

bitvec TableFormat::Use::no_overhead_atcam_result_bus_words

(

)

const

For ATCAM specifically, only one result bus is allowed per match. This is due to the priority ranking. Each RAM can at most hold 5 entries, and those entries, numbered 0-4 are ranked in a priority.

Because multiple entries could potentially match within an ATCAM table, (unlike exact or proxy hash), the entry with the highest priority (i.e. 4 > 3) will win.

Other rules apply to these priority structures. Entries 0 and 1 are the only entries allowed to be shared across multiple RAMs. This is described in uArch section 6.4.3.1 Exact Match Physical Row Result Generation, and by the register match.merge.col.hitmap_ouptut.

Thus in order to maintain sanity, the entries published in the table format are numbered 0 .. highest entries <= 4. The numbered entries are the priority ranking of these entries, specifically only for ATCAM.

When the ATCAM table has overhead, the result bus is easy to determine. However, when there is no overhead, the result bus is more difficult and must be wherever any entry 2-4 resides.

This matches bf-asm function

result_bus_words()

bitvec TableFormat::Use::result_bus_words

(

)

const

Result buses are required by SRAM based tables to get data from the RAM to match central. This includes both overhead data, and vpn based data. The result bus itself is an 83 bit bus, 64 bits for bits 0-63 of the RAM line that matches, and 19 bits for a direct address location.

The rules of result bus requirements for each RAM word (an 128 bit section of RAM)

1. If a word has overhead of any entry, then a result bus is required for that word
2. If no entries have overhead, then any portion of each entries match must have a result bus. If an entry is within a single RAM section, then this RAM requires a result bus. If an entry is split across multiple RAMs, then one of those words requires a result bus

This matches the considerations in bf-asm/sram_match/verify_format and bf-asm/sram_match/no_overhead_determine_result_bus_words

Member Data Documentation

ghost_bits

std::map<IXBar::Use::Byte, bitvec> TableFormat::Use::ghost_bits

The byte and individual bits to be ghosted. Ghost bits should be the same for all match entries.